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| DS3816C-512 16Mb Advanced NV SRAM with Clock www.maxim-ic.com FEATURES 5V operation 10% Surface-mount NV RAM BGA module construction 512k x 32 NV SRAM memory space and separate 64 x 8 real-time clock memory space Real-time clock maintains hundredths of seconds, seconds, minutes, hours, day, date, month and year with leap year compensation valid up to 2100 Removable backup power source provides more than 8 years of timekeeping and data retention Read and write access times as fast as 70ns for NV SRAM memory and 150ns for real-time clock Automatic data protection during power loss Unlimited write cycle endurance Low-power CMOS operation Battery monitor checks remaining capacity daily Industrial temperature range of -40C to +85C PACKAGE OUTLINE Top View Bottom View Side View DESCRIPTION The DS3816C-512 is a 524,288 x 32-advanced nonvolatile (NV) SRAM module with a 168-bump ball grid array (BGA) pinout. The highly integrated DS3816C-512 contains a 64-byte real time clock, four 8Mb SRAMs and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the DS3816C-512 makes use of an attached DS3802 Battery Cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS3816C-512 has dedicated circuitry for monitoring the status of VCC and the status of an attached DS3802 Battery Cap. 1 of 16 08/12/02 DS3816C-512 PIN ASSIGNMENT Figure 1 (Top View) Because the DS3816C-512 has a total of 168 balls and only 75 active signals, balls are wired together into numbered groups, thus providing redundant connections for every signal. CEC OE WEC WE1 CE1 OEC CE3 A10 A11 A8 A9 A0 WE3 A1 A2 A3 A4 VCC 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 CEO 78 VCC BW 80 79 VBAT GND A15 A17 A13 A18 WE0 A16 A14 A12 A7 A6 A5 DQ7 DQ6 DQ5 RSV2 DQ4 DQ0 DQ1 DQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 RECEPTACLES FOR DS3801 DS3802 BATTERY CAP PINS 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 CE2 DQ31 DQ30 DQ29 WE2 DQ28 DQ27 DQ24 DQ25 DQ26 DQ16 DQ17 DQ18 DQ23 RSV1 DQ22 DQ21 DQ20 DQ19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND GND DQ3 DQC3 DQC4 DQC5 NC DQC6 DQC7 DQC0 DQC1 DQC2 DQ10 DQ9 DQ8 DQ15 INT DQ14 DQ13 DQ12 DQ11 GND VBAT PIN DESCRIPTION A18- A0 DQ31 - DQ0 DQC7-DQC0 CE3 - CEO CEC WE3 WEC OE - WEO - Address Inputs NV SRAM Data In/Data Out Clock Data In/Data Out NV SRAM Chip Enable Inputs Clock Chip Enable Input NV SRAM Write Enable Inputs Clock Write Enable Input NV SRAM Output Enable Input BW INT VCC GND RSV1 RSV2 VBAT OEC - Battery Warning Output - Interrupt Output - Power (5V) - Ground - No Connect - No Connect - DS3802 Battery Cap Connection - Clock Output Enable Input 2 of 16 DS3816C-512 BLOCK DIAGRAM Figure 2 DS3802 3 of 16 DS3816C-512 NV SRAM READ MODE The DS3816C-512 executes an NV SRAM read cycle whenever WE0 - WE3 (Write Enables) are inactive (high), any or all of CE0 - CE3 (Chip Enables) are active (low) and 0E (Output Enable) is active (low). The unique address specified by the 19 address inputs (A0 - A18) defines which of the 524,288 words of data is accessed. The four chip enable signals ( CE0 - CE3 ) determine which bytes in the addressed word are output on data lines DQ31 - DQ0. Valid data will be output within tACC (NV SRAM Access Time) after the last address input signal is stable, providing that CE and 0E (Output Enable) access times are also satisfied. If CE and 0E access times are not satisfied, then data access must be measured from the later occurring signal ( CE or 0E ) and the limiting parameter is either tCO for CE or tOE for 0E rather than tACC. NV SRAM WRITE MODE The DS3816C-512 executes an NV SRAM write cycle whenever any or all of the WE signals ( WE0 - WE3 ) are active (low) and any of the corresponding CE signals ( CE0 - CE3 ) are active (low) after all address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept valid throughout the write cycle. WE0 - WE3 must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The 0E control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if output drivers are enabled ( CE and 0E active) then WE will disable the outputs in tODW from its falling edge. CLOCK READ MODE The DS3816C-512 executes a clock read cycle whenever WEC (Clock Write Enable) is inactive (high), CEC (Clock Chip Enable) is active (low) and OEC (Output Enable) is active (low). The unique clock address specified by address inputs A0 - A5 defines which of the 64 bytes of data is accessed. Valid data will be output within tACC (Clock Access Time) after the last address input signal is stable, providing that CEC and OEC (Output Enable) access times are also satisfied. If CEC and OEC access times are not satisfied, then data access must be measured from the later occurring signal ( CEC or OEC ) and the limiting parameter is either tCO for CEC or tOE for OEC rather than tACC. Only addresses 0 to 3 FH are implemented in the clock address space. Accesses to clock addresses higher than 3 FH are undefined. CLOCK WRITE MODE The DS3816C-512 executes a clock write cycle whenever WEC is active (low) and CEC is active (low) after all address inputs are stable. The later occurring falling edge of CEC or WEC will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CEC or WEC . All address inputs must be kept valid throughout the write cycle. WEC must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The OEC control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if output drivers are enabled ( CEC and OEC active) then WEC will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS3816C-512 provides full functional capability for VCC greater than 4.5V and write protects by 4.25V. Data is maintained in the absence of VCC without any additional support circuitry. The DS3816C-512 constantly monitors VCC. Should the supply voltage decay to VTP, the device automatically write protects itself, all inputs become "don't care," and all outputs become high impedance. As VCC falls below approximately 2.7V, a power switching circuit electrically connects an 4 of 16 DS3816C-512 attached DS3802 Battery Cap to the SRAM to retain data. During power-up, when VCC rises above approximately 2.7V, the power switching circuit connects external VCC to the SRAM and disconnects the DS3802. Normal RAM operation can resume after VCC exceeds 4.5V. BATTERY MONITORING The DS3816C-512 automatically monitors the battery in an attached DS3802 Battery Cap on a 24-hour time interval. Such monitoring begins within tREC after VCC rises above VTP and is suspended when power failure occurs. After each 24-hour period has elapsed, the battery is connected to an internal 1MW test resistor for one second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the battery warning output BW is asserted. Once asserted, BW remains active until the battery cap or DS3802 is replaced. The battery is still retested after each VCC power-up, however, even if BW is active. If the battery voltage is found to be higher than 2.6V during such testing, BW is a de-asserted and regular 24-hour testing resume. BW has an open-drain output driver. CLOCK REGISTERS Figure 3 5 of 16 DS3816C-512 TIME OF DAY ALARM MASK BITS Figure 4 REGISTER MINUTES HOURS 1 1 0 1 0 0 0 0 DAYS 1 1 1 0 ALARM ONCE PER MINUTE ALARM WHEN MINUTES MATCH ALARM WHEN MINUTES AND HOURS MATCH ALARM WHEN MINUTES, HOURS AND DAYS MATCH NOTE: Any other bit combinations produce illogical operation. CLOCK REGISTERS The DS3816C-512 clock has 14 8-bit internal registers that contain all timekeeping, alarm, watchdog, and control information. The clock, calendar, alarm, and watchdog registers are memory locations that contain both external (user accessible) and internal copies of the data. The external copies are independent of internal functions except that they are updated periodically by simultaneous transfer from the incremented internal copies. The Command Register bits are affected by both internal and external functions. In addition to the 14 registers, the clock also contains 50 bytes of user RAM. Clock registers 0, 1, 2, 4, 6, 8, 9, and A (hex) contain day, date, and time information stored in binary-code decimal (BCD) format. Registers 3, 5, and 7 contain time-of-day alarm information also stored in BCD format. Register B is the Command Register containing eight 1-bit binary fields. Registers C and D contain watchdog alarm information stored in BCD format. Addresses E through 3F are general-purpose user RAM. DAY, DATE AND TIME REGISTERS Registers 0, 1, 2, 4, 6, 8, 9, and A (hex) contain day, date and time information in BCD format. Eleven bits within these eight registers are not used and will always read zero regardless of how they are written. Bits 6 and 7 in the Month Register (register 9) are binary control bits. When set to logic 0, EOSC (register 9, bit 7) enables the clock oscillator. This bit will normally be turned on by the user during device initialization. The oscillator can be turned on and off as needed by enabling or disabling this bit. Register 9, bit 6, ESQW , enables and disables the output of a 1024Hz square wave. Because this feature is not supported in the DS3816C-512, ESQW should be set to logic one. Bit 6 of the Hour Register (register 4) is defined as the 12- or 24-Hour Select Bit. When set to logic one, the 12-hour format is selected. In the 12-hour format, bit 5 is the AM/PM bit with logic 1 being PM. In the 24-hour mode, bit 5 is the upper-order 10-hour bit (set for hours 20-23). The external day, date, and time registers are updated from their internal counterparts every 0.01 seconds except when the TE bit (bit 7 of register B) is set low or the clock oscillator is not running ( EOSC high). Setting TE low will freeze the external day, date, and time registers at their present values allowing all the registers to be read or written without any of them being updated from the internal registers. After the registers have been read or written, setting TE high will re-enable external register updates. While TE is set low and the external registers are frozen, the internal registers continue to be incremented. 6 of 16 DS3816C-512 TIME OF DAY ALARM REGISTERS Registers 3, 5, and 7 contain the Time of Day Alarm registers. Bits 3, 4, 5, and 6 of register 7 will always read zero regardless of how they are written. Bit 7s of registers 3, 5, and 7 are mask bits (Figure 4). When all of the mask bits are logic 0, a time of day alarm will only occur when registers 2, 4, and 6 match the values stored in registers 3, 5, and 7. An alarm will be generated every day when bit 7 of register 7 is set to logic 1. Similarly, an alarm is generated every hour when registers 7 and 5 both have bit 7 set to logic 1. When registers 7, 5 and 3 all have bit 7 set to logic 1, an alarm will occur every minute at the point where register 1 (seconds) rolls over from 59 to 00. Whenever an alarm occurs, the Time of Day Alarm Flag TDF (register B bit 0) and the internal Time of Day Interrupt signal will go to the active state. If the Interrupt Switch bit IPSW (register B bit 6) is set to a logic 0 and the Time of Day Alarm Mask bit TDM (register B bit 3) is logic 0, the Interrupt Output pin INT will also activate. Time of day alarm registers are written and read in the same format as the day, date, and time registers. The Time of Day Alarm Flag, Time of Day Interrupt and INT output are always cleared when the Time of Day Alarm registers are read or written. WATCHDOG ALARM REGISTERS Registers C and D contain the timeout period for the Watchdog Alarm. The two registers contain a count from 0.01 to 99.99 seconds in BCD format. The two Watchdog Alarm Registers can be written or read in any order. After a new value is entered or either of the Watchdog Alarm Registers is read, an internal watchdog timer will start counting down from the entered Watchdog Alarm Register value toward zero. When zero is reached, the Watchdog Alarm Flag (register B, bit 1) and the internal Watchdog Interrupt signal will go to the active state. If the Interrupt Switch bit IPSW (register B, bit 6) is set to logic 1 and the Watchdog Alarm Mask bit WAM (register B, bit 3) is logic 0, the Interrupt Output INT will also activate. The watchdog timer countdown is interrupted and the timer is re-initialized to the value in the Watchdog Alarm Registers every time either Watchdog Alarm Register is accessed. Controlled, periodic accesses to the Watchdog Alarm Registers can prevent the activation of the Watchdog Alarm Flag, the internal Watchdog Interrupt signal and the INT output. The Watchdog Alarm Registers always read the value entered. The actual watchdog timer is internal and is not accessible. Writing 00H to registers C and D will disable the Watchdog Alarm feature. COMMAND REGISTER Register B, the Command Register, contains control bits and flag bits. The operation of each bit is described below. TE - Transfer Enable (bit 7) When set to logic 0, this bit disables the transfer of data between internal and external clock registers. The contents of the external registers are frozen and reads and writes of day, date and time information are not affected by updates. This bit must be set to logic 1 to enable updates. IPSW - Interrupt Switch (bit 6) This bit should be initialized to logic 1 to connect the internal Watchdog Interrupt signal to the INT output pin. Setting this bit to logic 0 connects the internal Time of Day Interrupt signal to the INT output pin. HI/LO - INT Sink or Source Current (bit 5) When this bit is set to logic 1 and VCC is applied, the INT output pin will source current when activated (see IOH spec). When this bit is set to logic 0, INT will sink current (see IOL spec). 7 of 16 DS3816C-512 PU/LVL - INT Pulse or Level (bit 4) When this bit is set to logic 0, INT will be in the level mode, going to the logic level define by the HI/LO bit and staying there until the interrupt is cleared. When this bit is set to logic 1, INT will be in pulse mode, sourcing or sinking current as defined by the HI/LO bit for a minimum of 3ms and then releasing. WAM - Watchdog Alarm Mask (bit 3) When this bit is set to logic 0, the internal Watchdog Interrupt signal will be enabled. If IPSW is also set to logic 1, any Watchdog Alarm will activate the INT output. When this bit is set to logic 1, Watchdog Alarms will have no effect on the internal Watchdog Interrupt signal or on the INT pin. TDM - Time of Day Alarm Mask (bit 2) When this bit is set to logic 0, the internal Time of Day Interrupt signal will be enabled. If IPSW is set to logic 0, any Time of Day Alarm will activate the INT output. When this bit is set to logic 1, Time of Day Alarms will have no effect on the internal Time of Day Interrupt signal or on the INT pin. WAF - Watchdog Alarm Flag (bit 1) This bit is set to logic 1 when a Watchdog Alarm occurs (regardless of the state of the Watchdog Alarm Mask bit WAM). WAF is read-only. This bit is reset when either of the Watchdog Alarm Registers is accessed. When the PU/LVL bit is in the pulse mode, this flag will only be set to logic 1 for the 3 ms duration of the INT output pulse. TDF - Time of Day Alarm Flag (bit 0) This bit is set to logic 1 when a Time of Day Alarm occurs (regardless of the state of the Time of Day Alarm Mask bit TDM). TDF is read-only. The time the alarm occurred can be determined by reading the Time of Day Alarm Registers. This bit is reset to logic 0 when any of the Time of Day Alarm Registers is accessed. When the PU/LVL bit is in the pulse mode, this flag will only be set to logic 1 for the 3ms duration of the INT output pulse. 8 of 16 DS3816C-512 ABSOLUTE MAXIMUM RATINGS* Voltage on any pin relative to ground Operating temperature Storage temperature Soldering temperature -0.3 to +6.0 V -40C to 85C -40C to 85C See J-STD-020A specification * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER Power Supply Voltage Logic 1 Input Voltage Logic 0 Input Voltage SYMBOL VCC VIH VIL MIN 4.5 2.2 0 TYP 5.0 (TA = -40C to 85C) MAX 5.5 VCC 0.8 UNITS V V V NOTES DC ELECTRICAL CHARACTERISTICS PARAMETER Input Leakage Current I/O Leakage Current Output Current @ 2.4V Output Current @ 0.4V Standby Current (all CE =VIH) Standby Current (all CE =VCC-0.3V) Operating Current (one CE =VIL) Operating Current (all CE =VIL) Write Protection Voltage SYMBOL IIL IIO IOH IOL ICCS1 (TA = -40C to 85C; VCC= 5V10%) MIN -5 -1 -1 2.1 TYP MAX 5 1 UNITS mA mA mA mA mA NOTES 3 2 7 4 85 350 4.5 ICCS2 ICCO1 ICCO2 VTP mA mA mA V 3 3 4.25 4.37 CAPACITANCE PARAMETER Input Capacitance: A18-A0, OE Input Capacitance: CE3 - CE0 , WE3 WE0 , CEC , WEC , OEC I/O Capacitance: DQ31-DQ0, DQC7-DQC0 Output Capacitance: BW , INT SYMBOL CIN MIN TYP 25 MAX 50 (TA = 25C) UNITS pF NOTES CIN CI/O COUT 5 5 5 10 10 10 pF pF pF 9 of 16 DS3816C-512 AC ELECTRICAL CHARACTERISTICS PARAMETER Read Cycle Time Access Time OE to Output Valid CE to Output Valid OE or CE to Output Active Output High-Z from Deselection Output Hold from Address Change Write Cycle Time CE Pulse Width Write Pulse Width Address Setup Time SYMBOL tRC tACC tOE tCO tCOE (TA = -40C to 85C; VCC = 5V10%) CLOCK MIN MAX 150 150 70 150 5 UNITS ns ns ns ns ns NOTES NV SRAM MIN MAX 70 70 35 70 5 5 5 tOD tOH tWC tCW tWP tAW tWR1 tWR2 tODW tOEW tDS tDH1 tDH2 5 70 55 55 0 5 12 25 5 150 150 100 0 10 10 25 5 30 0 7 5 60 0 0 50 ns ns ns ns ns ns ns ns ns ns ns ns Write Recovery Time Output High-Z from WE Output Active from WE Data Setup Time Data Hold Time 50 11 12 5 5 4 11 12 TIMING DIAGRAM: READ CYCLE 10 of 16 DS3816C-512 TIMING DIAGRAM: WRITE CYCLE 1 ( WE ) TIMING DIAGRAM: WRITE CYCLE 2 ( CE ) 11 of 16 DS3816C-512 POWER-DOWN/POWER-UP CONDITION See Note 10 TIMING DIAGRAM: BATTERY WARNING DETECTION See Note 13 12 of 16 DS3816C-512 POWER-DOWN/POWER-UP TIMING PARAMETER VCC Fail Detect to CE and WE Inactive VCC Slew from VTP to 0V VCC Slew from 0V to VTP VCC Valid to CE and WE Inactive VCC Valid to End of Write Protection VCC Valid to BW Valid INT Pulse Width (PU/LVL bit high) SYMBOL MIN TYP (TA = -40C to 85C) MAX UNITS ms ms ms ms ms s ms NOTES tPD tF tR tPU tREC tBPU tIPW 300 300 0 10 2 125 1 3 13 14 BATTERY WARNING TIMING PARAMETER Battery Test Cycle Battery Test Pulse Width Battery Test to BW Active SYMBOL tBTC tBTPW tBW (TA = -40C to 85C; VCC = 5V10%) MIN TYP 24 MAX 1 1 UNITS hr s s NOTES (TA = 25C) PARAMETER Expected Data Retention Time SYMBOL tDR MIN 8 TYP MAX UNITS years NOTES 9 WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: 1. 2. 3. 4. 5. 6. is high throughout read cycle. OE = VIH or VIL. If OE = VIH during write cycle, the output buffers remain in a high impedance state. All outputs open-circuited. tDS is measured from the earlier of CE or WE going high. These parameters are sampled with a 5pF load and are not 100% tested. If the CE low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a high impedance state during this period. 7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a high impedance state during this period. 8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high impedance state during this period. 9. Expected data retention time can be extended indefinitely if the DS3802 Battery Cap is periodically replaced. 10. In a power down condition the voltage on any pin may not exceed the voltage on VCC. 11. tWR1, tDH1 are measured from WE going high. 12. tWR2, tDH2 are measured from CE going high. 13. BW are open-drain outputs and cannot source current. External pull-up resistors should be connected to these pins for proper operation. Both pins will sink 10mA. 14. INT will activate within 100ns after the alarm condition arises. WE 13 of 16 DS3816C-512 DC TEST CONDITIONS Outputs Open All voltages are referenced to ground AC TEST CONDITIONS Output load: 100pF + 1 TTL gate Input pulse levels: 0V to 3.0V Timing measurement reference levels input: 1.5V output: 1.5V Input pulse rise and fall times: 5ns DS3816C-512 PACKAGE DIMENSIONS A B C D E F G H I J K DIM in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm in mm MIN 1.720 43.69 1.720 43.69 0.108 2.74 1.497 38.02 0.047 1.19 0.108 2.74 0.047 1.19 0.305 7.74 0.125 3.10 0.025 0.64 MAX 1.730 43.94 1.730 43.94 0.118 3.00 1.503 38.18 0.053 1.35 0.118 3.00 0.053 1.35 0.320 8.13 0.135 3.43 .135 3.43 0.032 0.76 14 of 16 DS3816C-512 DS3816C-512 PACKAGE DIMENSIONS (With Attached DS3802 Battery Cap) DIM in A mm in B mm in C mm in D mm MIM MAX 1.830 45.046 1.830 45.046 0.435 10.708 0.0390 0.9600 15 of 16 DS3816C-512 DS3816C-512 RECOMMENDED LAND PATTERN (With Overlaid Package Outline) The DS3816C-512 ball grid array is a subset of the industry-standard 40mm BGA format, with all balls on a 50mil grid. Corner balls have been removed to provide space for the electrical and mechanical interface features that facilitate attachment of the DS3802 Battery Cap. V-BAT TEST PADS 0.027 DIA 2 PL I/O PADS 0.27 DIA X 168 PL 0.113 0.150 80 79 78 7776 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 0.050 TYP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1.500 1.725 sq. 20 21 22 23 24 25 26 27 28 29 3031 32 33 34 35 36 3738 39 40 0.413 0.050 TYP 0.113 0.150 16 of 16 |
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